Encyclopedia of RF and Microwave Engineering , 6-Volume Set by Kai Chang

By Kai Chang

RF and Microwave Engineering is without doubt one of the quickest progress components of the previous decade and may most likely stay a truly energetic region of analysis and alertness in a wide number of fields. The six quantity set of Encyclopedia of RF and Microwave Engineering illustrates how this box has been the main to permitting expertise accountable for the outstanding development of instant communications. This set additionally examines how RF and microwave engineering keeps to have nice impact because the expertise in the back of such very important purposes as radar, distant sensing, handheld remote control, sensors, navigation, surveillance, digital conflict, radiometers, plasma examine, and imaging.

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  • AAP Awards for Excellence in expert and Scholarly Publishing, 2006

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Timing diagram of a pipelined ADC. A/D AND D/A CONVERSION ARCHITECTURES AND TECHNIQUES 13 2 Vi−1 1 C2 1 C1 1 − + Vi + − 2Di 2Di Figure 21. Switched-capacitor (SC) 1-bit pipeline stage (f1-sampling phase, f2-multiply-by-2/subtract phase). Di Vref −Vref Each stage consists of two nominally equal capacitors C1 and C2, an operational amplifier (op-amp), and a comparator. During the sampling phase f1, the comparator produces a digital output Di by comparing its input ViÀ1 with comparator threshold Vth ( 1 if ViÀ1 !

A pipelined converter therefore exhibits a concurrent nature of processing of input, enabling highspeed operation. As mentioned earlier, the complexity of the pipeline, measured in the number of stages, scales linearly with the desired resolution and therefore pipelined A/D converters show substantial power and area savings for high-resolution applications at high speed. In the pipeline architecture, as in all multistage ADC, the most significant bits are resolved by the stages earlier in the pipeline and the least significant bits are resolved later in the pipeline.

Comparing the number of comparators needed in the two-step architecture versus the flash architecture, we can see that significant area savings can be achieved. An 8-bit flash ADC will require 256 comparators, whereas a two-step ADC, with a 4-bit MSB stage and a 4-bit LSB stage, will need only 32 comparators, which is a significant savings in the area. However, the speed of the two-step converter is less than that of a pure flash A/D converter, due to additional delays introduced by the D/A converter and the subtractor.

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