By Andrea Leonardo Lacaita, Salvatore Levantino, Carlo Samori
The more and more hard functionality standards of communications structures, in addition to difficulties posed by way of the continuing scaling of silicon know-how, current various demanding situations for the layout of frequency synthesizers in glossy transceivers. This publication comprises every little thing you must comprehend for the effective layout of frequency synthesizers for modern day communications functions. if you would like to optimize functionality and reduce layout time, you'll find this e-book important. utilizing an intuitive but rigorous method, the authors describe easy analytical tools for the layout of part locked loop (PLL) frequency synthesizers utilizing scaled silicon CMOS and bipolar applied sciences. the full layout strategy, from system-level specification to format, is roofed comprehensively. useful layout examples are incorporated, and implementation matters are addressed. A key problem-solving source for practitioners in IC layout, the booklet may also be of curiosity to researchers and graduate scholars in electric engineering.
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Extra resources for Integrated Frequency Synthesizers for Wireless Systems
7), the unit-gain frequency may be estimated as ωu /2π ≈ (K VCO /2π ) · (IP R) (2π N ). 2 V. This example is, somehow, oversimplified. For instance, the value of the tuning constant K VCO is too high for a realistic implementation and a reduction of an order of magnitude would be needed. 5). Moreover, as has already been mentioned, the noise of both input stages and the VCO depends on loop parameters, such as K VCO and the CP current. After these parameters have been set, the noise densities should be evaluated again.
R Input phase noise (due to CP, divider, PFD) S OL ( f ) ∼ = −150 dBc/Hz. φ,IN r VCO phase noise S ∼ φVCO (1 MHz) = −120 dBc/Hz. r Noise corner2 = 200 kHz. 5 V. In an integer-N PLL, the frequency resolution, 10 MHz, sets the reference frequency. 5 V voltage range. The PLL bandwidth is set to the frequency at which the amplified input noise and the VCO noise cross each other. Taking N = 585, the input noise is amplified by 20 · log10 (N ) ≈ 55 dB and becomes about −95 dBc/Hz at the output. The VCO phase noise is −120 dBc/Hz 2 At the noise corner, the slope of the phase noise spectrum changes from f −2 to f −3 .
C. and the third pole, the capacitive division [C1 /(C1 + C2 )]2 is practically equal to one and the voltage noise from R is directly fed to the tuning node. 15). s. s. 4 from the various noise sources: thermal noise from the loop filter (circles), input white noise from CP, PFD and divider (triangles) and VCO noise (squares). The total spectrum is represented by the solid thicker line noise has a +40 dB/decade slope. Instead, at frequencies higher than the PLL bandwidth, the noise density at Vtune decreases as −20 dB/decade and HP is equal to one.