By Thomas M. Frederiksen
In engineering electronics this can be the period of very large-scale integration (VLSI). this is often the 1st authoritative textual content to track the $64000 steps within the evolution of IC processes-from the early p-channel MOS expertise, via PMOS and NMOS, to the state-of-the-art in CMOS VLSI. Concurrent advances in wafer fabrication also are defined. the sensible applications-of regular circuits, customized ICs, and excessive lead count number IC applications, for example-are then tested from the viewpoint of providers and shoppers. the writer additionally scans the recent frontiers: the potential for new electronic architectures, silicon circuits, VLSI software program and gallium arsenide ICs-An very good sourcework in the event you layout, produce, buy and paintings with digital expertise.
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Extra resources for Intuitive CMOS Electronics (The McGraw-Hill Series in Intuitive IC Electronics)
A process modification has been used to solve this contamination problem. It is called Field Threshold Adjustment. The basic idea is to add a final N-implant step near the end of the process. This implant is used to carefully increase the surface doping concentration of the N-epi without significantly reducing the maximum operating voltage of the finished product. This richer surface doping is more difficult to invert, under parasitic P-channel MOS action and, therefore, linear circuits that incorporate Field Threshold Adjustment are less affected by stress testing in plastic packages.
Sometimes the desired signal in a linear system is only 1 /LV. This is the reason that much care has to be taken to keep the many natural and man-made sources of electrical noise from contaminating linear circuits. Background on Solid-State Electronics 11 Silicon transistors have the characteristic of maintaining a low value of collector current at relatively large values of base-emitter ON voltages (400 mY). The silicon transistor has a useful, approximately ON-OFF thresholding or toggling feature that was not available with the smoother turn-ON at low base-emitter voltages that exists with a germanium transistor.
_ _ _ _ _--1. o VOUT Fig. 2-4 Voltage-Current Relationship of Various Logic Pull-Up Devices It is the dc current flow through the pull-up device. whether a resistor or a depletion-mode FET, when the output transistor is ON that causes dc current drain in bipolar, PMOS, and NMOS logic circuits. The usual assumption is that one-half of all of the logic circuits in a system will be in the dissipating ON state. As we will see later in this chapter. the novel gated load of CMOS logic circuits eliminates this static dc power drain.