Robust Computing with Nano-scale Devices: Progresses and by Chao Huang (auth.), Chao Huang (eds.)

By Chao Huang (auth.), Chao Huang (eds.)

Although complementary metal-oxide semiconductor (CMOS) expertise will proceed dominating the electronic digital circuits for the following 10-15 years, a few grand demanding situations have emerged because the transistor dimension scales down. The emerging expenditures of semiconductor masks and fabrication pose fiscal boundaries to lithography. The quantum results and lengthening leakage energy commence surroundings actual limits on non-stop CMOS characteristic dimension shrinking.

The examine advances of leading edge nano-scale units have created nice possibilities to surpass the limitations confronted by means of CMOS expertise, which come with nanowires, carbon nanotube transistors, programmable molecular switches, resonant tunneling diodes, quantum dots, etc.

However, the good fortune of many nanotechnologies depends on the self-assembly fabrication technique to manufacture circuits. The stochastic self-assembly fabrication, regrettably, has low reliability with illness densities a number of orders of value better than traditional CMOS technology.

Robust Nano-Computing makes a speciality of a variety of problems with strong nano-computing, defect-tolerance layout for nano-technology at diversified layout abstraction degrees. It addresses either redundancy- and configuration-based equipment in addition to fault detecting concepts during the improvement of actual computation versions and instruments. The contents current an insightful view of the continued researches on nano-electronic units, circuits, architectures, and layout equipment, in addition to offer promising instructions for destiny research.

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A promising defect tolerance approach is one combining expensive but reliable gates with cheap but unreliable gates. One approach for increasing reliability of gates is by adding redundancy at the transistor-level implementation. In this chapter, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by a quadded-transistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation.

To compute the circuit failure probability, Fm , resulting from injecting m defective transistors, we use the following procedure: 1. Set the number of iterations to be performed, I , to 1,000 and the number of failed simulations, K, to 0. 2. Simulate the fault-free circuit by applying the test set T . 3. Randomly inject m transistor defects. 4. Simulate the faulty circuit by applying the test set T . 5. If the outputs of the fault-free and faulty circuits are different, increment K by 1. 6. Decrement I by 1 and if I is not 0 go to step 3.

This is proved with respect to stuck-open and stuck-short defects as bridge defects have equivalent behaviors to them as explained earlier. If there are only two defective transistors in a quadded-transistor structure, then we have four possible pairs of stuck-open and stuck short defects. In all cases, only one of those pairÂofÃdefects produces an error. 1 P /2 : 2 4 2 If we assume that three transistors are defective, then we have eight possible combinations of stuck-open and stuck short defects.

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